Integrated semiconductor memory devices, such as DRAM (dynamic random access memory) devices, comprise a memory cell array with memory cells for storing data items. In order to store a data item in a memory cell of the memory cell array, a write command is applied to a control terminal of the integrated semiconductor memory device. Furthermore, to select one of the pluralities of memory cells which are arranged in rows and columns inside the memory cell array an address is applied to the integrated semiconductor memory device. The data item which has to be written into the selected memory cell is applied to a data terminal.
The semiconductor memory device comprises receiver circuits for receiving signals externally applied to the integrated semiconductor memory device. A first receiver circuit is connected to the control terminal for receiving the control signal. A second receiver circuit is connected to the address terminal to receive the address signal. A third receiver circuit is connected to the data terminal to receive the data signal. The receiver circuits are usually designed as differential amplifier circuits.
FIG. 1 illustrates an embodiment of a differential amplifier circuit used as a receiver circuit in an integrated semiconductor memory device. The receiver circuit comprises a terminal for applying a power supply voltage and a terminal for applying a reference voltage, such as a ground potential. First and second current paths are connected in parallel between the terminal for applying the power supply voltage and a common terminal. The first current path comprises a first transistor and a first resistor which are connected in series between the terminal for applying the power supply voltage and the common terminal. The second current path comprises a second transistor and a second resistor which are connected in series between the terminal for applying the power supply voltage and the common terminal. A common current path which comprises a current source connects the common terminal with the terminal for applying the reference voltage. The current source generates a constant bias current.
A control terminal of the first transistor is used to apply a reference signal. A control terminal of the second transistor serves to apply an input signal. When the receiver circuit illustrated in FIG. 1 is provided in an integrated semiconductor memory device as a data input receiver, data signals which are externally applied to the integrated semiconductor memory device are transferred to the control terminal of the second transistor of the receiver circuit. When the receiver circuit is provided for receiving address signals, an address signal, which is externally applied to the integrated semiconductor memory device, actuates the control terminal of the second transistor of the receiver circuit. It is also possible to provide the receiver circuit for receiving command signals externally applied to the integrated semiconductor memory device for activating a read access or a write access to the memory cells of the integrated semiconductor memory device. In this case, the control terminal of the second transistor of the receiver circuit is driven by a command signal.
A memory module, such as a DIMM (Dual In Line Memory Module), comprises a plurality of integrated semiconductor memory devices. A dissipation loss of the module is dependent on the number of integrated semiconductor memories of the memory module. Another contributor to dissipation losses is leakage currents which occur in each of the receiver circuits of the integrated semiconductor memory devices. A high amount of the bias current causes an increased dissipation loss. However, a high amount of bias current also enables a reduced access time for read accesses and write accesses as the receiver sensitivity is dependent on the amount of bias current.
The DIMM can be used in different application fields wherein the integrated semiconductor memory devices arranged on a surface of a chip of the DIMM have different organization forms. Integrated semiconductor memory devices for notebook applications are usually designed in an organization form ×16. In the organization form ×16, a common access, to sixteen individual memory cells, is performed during a unique read access or write access. Integrated semiconductor memory devices organized in a configuration ×8 are provided for desktop applications. In the desktop mode a common access to eight memory cells during a unique read access or write access is enabled. For server applications, integrated semiconductor memory devices with an organization form ×4 are provided. In the organization form ×4, a common access to four memory cells during a unique read access or write access is enabled.
For desktop applications as well as for notebook applications the access time is an important matter. For server applications an important performance feature of a module is the memory density, i.e., the number of integrated semiconductor memory devices arranged on a chip of the module.
Up until now, the receiver circuits of integrated semiconductor memory devices have been designed to afford a high speed access to the memory cells. That means that the current source is designed to generate a high amount of bias current. As a consequence, when integrated semiconductor memory devices comprising receiver circuits that are configured as differential amplifier circuits such as shown in FIG. 1 and are operated with a high amount of bias current, a high dissipation loss occurs. High density semiconductor memory modules with a memory capacity of 4, 8 or 16 Gigabyte have a dissipation loss or a thermal design power of 10 Watt or more.
The high dissipation loss leads to a high temperature of the memory module. To decrease the high temperature of the module it is required to arrange a plurality of fans on the chip of the memory module. Another problem occurs if the memory cell array of the integrated semiconductor memory device comprises DRAM cells. For a memory module comprising such memory cells, the high temperature leads to retention problems.
Therefore, it is desired to decrease the high temperature of the integrated semiconductor memory device or the memory module. A further possibility to reduce the high temperature is to decrease the clock frequency of the memory module. However, the reduction of clock frequency as well as the use of ventilators leads to a deterioration of the cost/performance ratio of the integrated semiconductor memory devices or the memory module including such integrated semiconductor memory devices.